IBIS Macromodel Task Group

Meeting date: 26 October 2021

Members (asterisk for those attending):
Achronix Semiconductor:       Hansel Dsilva
Amazon:                       John Yan
ANSYS:                      * Curtis Clark
                            * Wei-hsing Huang
Cadence Design Systems:     * Ambrish Varma
                              Ken Willis
                              Jared James
Google:                     * Zhiping Yang
Intel:                        Michael Mirmak
                              Kinger Cai
                              Alaeddin Aydiner
Keysight Technologies:        Fangyi Rao
                            * Majid Ahadi Dolatsara
                              Ming Yan
                            * Radek Biernacki
                            * Rui Yang
                              Todd Bermensolo
Luminous Computing            David Banas
Marvell                       Steve Parker
Mathworks (SiSoft):         * Walter Katz
                              Mike LaBonte
Micron Technology:          * Randy Wolff
                            * Justin Butterfield
Missouri S&T                * Chulsoon Hwang
Siemens EDA (Mentor):       * Arpad Muranyi
Teraspeed Labs:             * Bob Ross
Zuken USA:                  * Lance Wang

The meeting was led by Arpad Muranyi.  Curtis Clark took the minutes.

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Opens:

- None.

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Review of ARs:

- Arpad to invite Chulsoon to present his GitHub model library proposal to ATM.
  - Done.

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Call for patent disclosure:

- None.

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Review of Meeting Minutes:

Arpad asked for any comments or corrections to the minutes of the October 19th
meeting.  Randy moved to approve the minutes.  Bob seconded the motion.
There were no objections.

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New Discussion:

Supporting PI modeling/simulation in IBIS:
Randy shared his presentation "Output Buffer PSIJ Analysis".  It presented
results from a simulation study performed on a Tx buffer to gather data and
provide input for a potential new BIRD.  The primary question is, how should a
device vendor go about measuring PSIJ?
- Are there load dependencies?
  - Tests were run on a 50 Ohm load into various values of VTT:
    - VSS
    - VDDQ (fixed at nominal)
    - VDDQ that varied as VDDQ was swept.
  - At what voltage level should the output timing shift be measured?
    - A fixed V or a VDDQ dependent value?
  - How to vary VSS, VDDQ, or both?
  - How does the test load measurement compare to measurement of the internal
    delay of the pre-driver logic gates?
- Should there be unique PSIJ values for pullup and pulldown?
- How linear is PSIJ?
  - Is a single s/V value sufficient, or do we need a table of values based on
    the magnitude of the VDDQ variation?
    
- What's the problem? (slides 4-6)
These slides show output waveforms from simulations with IBIS b-elements vs.
transistor-level models.  VDDQ is swept, and the slides show the results for
different values of VTT.  All slides show that IBIS does not capture the PSIJ.
A secondary issue was noted, the IBIS simulations with ISSO_PD and ISSO_PU
don't capture the Idrain-source variation captured in the transistor-level
model simulations.  (see explanation in Conclusion slide)

- slide 8: Pre-driver and Final Driver Schematic
This slide provides an abstract schematic representation.  Randy noted that
there is additional logic prior to that shown in the figure.  Some gates in the
pre-driver are in the same VDDQ domain as the main I/O driver.  Discussion of
the pre-driver delay refers to the delay through these pre-driver gates from
the input to the chain through to its output to the final I/O driver.

- slide 9: VDDQ swept from 0.85 - 1.35V, VTT variable (transistor-level model)
Randy noted that because the high to low swing into the test load is changing
significantly as VDDQ is swept, using a single fixed threshold voltage to
measure the timing delay may not be a good way to measure delay over the entire
sweep.  He suggested that we might want a threshold in the middle range of the
of the voltage swing (e.g., VTT = 0.75*VDDQ is shown as the measurement point
as VDDQ is swept).
    
slide 9 - 12 show waveform plots and plots of delay vs. VDDQ variation from
nominal.  The results are significantly different for VTT=VDDQ (fixed nominal)
vs. VTT=VDDQ (variable).

slide 13: VSS swept from -0.25 to 0.25V, VTT=VDDQ(fixed) or VTT=VSS
Randy said he had not thought much about the additional effects caused by
varying VSS, but he noted (referring back to slide 8) that additional gates
other than those on VDDQ would be affected as there is only 1 VSS domain.
Arpad asked if these plots were relative to ideal node 0 or the varying VSS.
Randy said the waveform plots were relative to node 0.

slide 15: Pullup/Pulldown Pre-Driver Delays
This slide shows plots of the pre-driver Input and Output waveforms (overlaid)
and the waveform at the pad (test load).  Randy noted that the pre-driver input
waveform is in the VDD domain and not affected by the VDDQ variations.

slides 17-20: PSIJ plots
These slides present plots of delays measured at the pad into various loads as
well as pre-driver delay characterization.  Randy noted that the pre-driver
delay curves were for 1 particular signal and averaged over several different
legs.  The curves were presented over +/- 250mV of VDDQ swing from nominal and
also zoomed in over a range of +/- 100mV from nominal.  Randy said the 100mV
range was sufficient to cover the variation in VDDQ allowed in the
specification.

Arpad asked what caused the slight waviness is some of the delay curves.  Randy
said he hadn't investigated that, but he thought the data was on 10mV
increments and it could be related to the fit to the data.  Randy noted that the
linear fit curve was for the pre-driver delay data.  He said that the pre-driver
delay is really the reference for this PSIJ measurement, and delay measurements
at all the other test loads were all over the place and didn't really match the
pre-driver delay curve.

Randy said that in thinking about a measurement that could be done for this PSIJ
value, it might make sense to take delay measurements at the test load for an
IBIS model, which we know doesn't have PSIJ in it, and subtract those from the
transistor-level simulations that do include the PSIJ.  With this difference
technique, you could take the data at any test load, and transistor-level
results minus IBIS results would yield a quantity that tracks the pre-driver
delay.

Conclusion Slide:
ISSO_PD in IBIS models modulate IDS based on changes in VGS, but only source
not gate voltage changes are considered.

Randy noted that timing should be measured at a % of VDDQ to adjust to relative
voltage swing at the test load.  Measurement thresholds should probably stay
within 20-80% of the voltage swing.  It may be best to use the datasheet timing
test load for the measurement.

To estimate pre-driver PSIJ, measure the power supply induced delay changes from
an IBIS model simulation into a test load and subtract them from transistor-
level model simulation results into the same test load.

PSIJ was not entirely linear across the voltage range, but the error to the
linear fit was < 2ps over the +/-100mV VDDQ variation.

Bob asked if these techniques would work with Open Source and Open Drain
devices.  Randy said he hadn't considered them, but he thought similar
techniques could be applied.

Arpad noted that when extracting V-T curves for IBIS models, when the load is
tied to high or tied to low you can see differences in the curves because of
the different turn on or turn off rates for the pullup and pulldown.  He asked
if those differences in on and off characteristics would affect the jitter
values seen in this study?  Randy said this was a good question.

Walter said that even if the standard allows 100mV variation, that is probably
more in terms of DC.  He said DC variation would contribute to pulse-width
distortion if the effect on rising/falling edges rates was different, but DC
offset would not cause jitter.  He said PSIJ is more of a high frequency issue,
perhaps driven by VDDQ changes at the frequency of the operating range of the
device.  Walter suggested the AC component might be 10 or 20mV.  Randy said
the AC component has a big dependence on the package inductance, so the
variation might be larger than Walter suggested.  Randy agreed that newer
DDR standards are tending to separate out the specifications of the limits for
DC and AC.

Majid asked if this PSIJ was independent of the random jitter parameters we
already have in AMI.  Randy said this PSIJ study was independent of random
jitter and from a different effect.  Majid referred to a webinar in which Todd
Bermensolo had been asked about whether AMI models could support power supply
noise.  Todd had replied that they could not handle it directly, but you could
possibly add the effects in via AMI jitter parameters.  Arpad said this PSIJ
discussion was about regular I-V and V-T curve based IBIS models.

GitHub Model Library proposal:
Chulsoon had agreed to present the GitHub demo first presented at the last Open
Forum meeting.  He and Zhiping had conceived of the idea as a new way for
vendors to distribute IBIS models.

Chulsoon showed the demo repository he had created.  He said that we could
create 4 different levels of access:
  - Public: anyone with or without a GitHub account
  - Company/Vendor Representative: outside collaborator who can upload models
    and manage changes to their models.
  - IBIS Experts: Expert collaborators and members of IBIS
  - Owners: own and manage the overall repository
  
Chulsoon said the site owner(s) could assign company representatives.  The
general public could download models and suggest changes (pull requests).  Each
model vendor's representative(s) would manage their own models and any pull
requests submitted for them.

Bob said we would need some sort of disclaimer.  Either we would state that the
company/author/organization is responsible for the accuracy of any models, or
we would state that IBIS is not responsible for the accuracy.  Arpad agreed that
we would be stating that these models are not approved and endorsed by IBIS.
Zhiping suggested that we might be able to provide a pop-up dialog presenting
the download agreement and requiring the user to accept.

Ambrish said this was a great idea for IBIS model users and EDA vendors.
However, he asked if we had polled model vendors to see how open they would be
to publishing anything in an open-source repository.  Zhiping said it might
be worth surveying the IBIS members to see how many would be willing to publish
models in this repository.  Arpad asked if we could use this as a mechanism to
distribute models, even if the user might need an NDA key or some other means
of using them.  Wei-hsing said that with the free GitHub platform the default is
open source, but if you have a private project you can pay extra for additional
features.  Randy said he liked this idea most as a place where people could
download reference examples for which there were no IP concerns.
(For more information, also see the Open Forum minutes from October 8, 2021)

- Ambrish: Motion to adjourn.
- Curtis: Second.
- Arpad: Thank you all for joining.

AR:  Randy to send his PSIJ data presentation to ATM.

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Next meeting: 02 November 2021 12:00pm PT
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IBIS Interconnect SPICE Wish List:

1) Simulator directives
